A High-Performance 64-bit Adder Implemented in Output Prediction Logic

Output Prediction Logic (OPL) is a technique that can be applied to conventional CMOS logic families to obtain considerable speedups. When applied to static CMOS, OPL retains the restoring character of the logic family. Speedups of 2x10 3X over (optimized) conventional static CMOS are demonstrated for a variety of circuits, ranging from chains of gates, to datapath circuits, and to random logic benchmarks. Such speedups are obtained using identical netlists without remapping. When applied to pseudo-nMOS and dynamic families in combinarion with remapping to wide-input NORs, OPL yields even greater speedups over static CMOS. In this paper we present a novel 64-bit adder design implemented in OPL using a combination of %bit Carry Look Ahead and Carry Select. The very fast wide-input OPL NORs enabled the use of 8-bit C U units instead of the usual 4-bit. Using a process-independent metric for comparison, this adder is twice as fast as previously published 64-bir adders.